In recent years, with the increasing demand for a higher-performance transistor, it has been difficult to sufficiently improve the performance of a transistor only by miniaturizing the transistor. For this reason, new techniques are being employed. In one of such new techniques, the performance of a transistor is improved by applying a stress to its channel to increase the career (electron or hole) mobility.
For example, U.S. Pat. No. 7,081,395 discloses a technique in which an insulating layer provided so as to surround an NMOS active region and a PMOS active region and to isolate these regions from each other so that a stress of the insulating layer can be applied to the regions.
In general, in an NMOS active region, the increase in the career (electron) mobility is obtained when a tensile stress is isotropically applied. By contrast, in a PMOS active region, the increase in the career (hole) mobility is obtained when a compression stress is anisotropically applied in only the channel length direction (direction in which current flows). In the structure according to U.S. Pat. No. 7,081,395, an insulating layer for applying a compression stress in the channel length direction to the PMOS active region is provided at ends, in the channel width direction (direction approximately perpendicular to the channel length direction), of the NMOS active region. As a result, the compression stress of the insulating layer is also applied in the NMOS active region, so that the career mobility in the NMOS active region may possibly be reduced.